Method for forming high-k charge storage device

ABSTRACT

Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.

CROSS REFERENCE TO RELATED APPLICATION

This application is a Continuation application which claims benefit ofco-pending U.S. patent application Ser. No. 11/039,430, filed Jan. 20,2005, which is hereby incorporated by reference in its entirety.

BACKGROUND OF INVENTION

1) Field of the Invention

This invention relates generally to the structure and fabrication ofsemiconductor devices and more particularly to the fabrication of adielectric materials for memory devices.

2) Description of the Prior Art

A key issue for floating-gate nonvolatile semiconductor memories (NVMs)is the scaling of the tunneling oxide because the stress-induced leakagecurrent (SILC) limits the tunnel oxide to ˜8 nm. This scaling issue is aformidable challenge especially for the emerging system-on-chip (SOC)integrated circuits designs in which programming voltage must be scaledfor the NVMs to be compatible with the low voltage logic circuits.Therefore, silicon-oxide-nitride-oxide-silicon (SONOS) charge-trappingbased NVM is replacing floating-gate NVM due to its advantages of lowerprogramming voltage, smaller cell size and better endurance over thefloating-gate devices. However, retention and erase speed remain as themajor challenges for conventional SONOS devices as device and voltagefurther scale in the future.

The relevant technical developments in the literature can be aredescribed below.

U.S. Pat. No. 6,803,275—Park, et al.—Oct. 12, 2004—NO fabricationprocess for reducing oxygen vacancy content in bottom oxide layer inflash memory devices.

U.S. Pat. No. 6,680,509—Wu, et al.—Nitride barrier layer for protectionof ONO structure from top oxide loss in fabrication of SONOS flashmemory.

U.S. Pat. No. 6,790,755—Jeon—Preparation of stack high-K gatedielectrics with nitrided layer.

Bunmi Adetutu, Jiankang Bu, Hsing Tseng, “A Novel Floating Trap NVSM”.

US 20030194853 A1—Jeon, Joong—Preparation of stack high-K gatedielectrics with nitrided layer.

U.S. Pat. No. 6,764,898B1—En et al.—shows a SONOS device with High klayers.

US 20030219947—Shin, Yoo-Cheol—Memory device and fabrication methodthereof.

U.S. Pat. No. 6,740,605B1—Shiraiwa et al. shows a SONOS like device.

SUMMARY OF THE INVENTION

The embodiments of the present invention provides a structure and amethod of manufacturing a memory device.

A first embodiment of a method of fabrication of a floating gatenon-volatile memory device comprising the following steps:

-   -   forming a bottom tunnel layer over a substrate; the bottom        tunnel layer comprised of a lower oxide tunnel layer and a upper        hafnium oxide tunnel layer;    -   in a tunnel anneal step, annealing the bottom tunnel layer in a        hydrogen containing atmosphere;    -   forming a charge storage layer over the bottom tunnel layer;    -   in a storage anneal step, annealing charge storage layer over        the bottom tunnel layer in a nitrogen containing atmosphere;    -   forming a lower hafnium oxide storage layer over the charge        storage layer;    -   in a block anneal step, annealing the top blocking layer in a        nitrogen containing atmosphere;    -   forming an upper cap oxide storage layer over the lower hafnium        oxide storage layer; The lower hafnium oxide storage layer and        an upper oxide storage layer form a top blocking layer;    -   forming a gate electrode over the top blocking layer;    -   patterning the bottom tunnel layer; the charge storage layer;        and top blocking layer to form a gate structure;    -   forming source/drain regions in the substrate adjacent to the        gate structure.

A second embodiment of a method of fabrication of a floating gatenon-volatile memory device comprising the following steps:

-   -   forming a bottom tunnel layer over a substrate;        -   in a tunnel anneal step, annealing the bottom tunnel layer            in a hydrogen containing atmosphere;    -   forming a charge storage layer over the bottom tunnel layer;    -   in a storage anneal step, annealing charge storage layer in a        nitrogen containing atmosphere;    -   forming a top blocking layer over the charge storage layer;    -   in a block plasma nitridation step, annealing the top blocking        layer in a nitrogen containing atmosphere;    -   forming a gate electrode over the top blocking layer;    -   patterning the bottom tunnel layer; the charge storage layer;        and top blocking layer and the gate electrode to form a gate        structure;    -   forming source/drain regions in the substrate adjacent to the        gate structure;

An example first device embodiment of a floating gate non-volatilememory device comprises:

-   -   a bottom tunnel layer over a substrate; the bottom tunnel layer        comprised of a lower oxide tunnel layer and a upper hafnium        oxide tunnel layer;    -   a charge storage layer over the bottom tunnel layer;    -   a lower hafnium oxide storage layer over the charge storage        layer;    -   an upper cap oxide storage layer over the lower hafnium oxide        storage layer; the a lower hafnium oxide storage layer and an        upper oxide storage layer form a top blocking layer;    -   a gate electrode over the top blocking layer;    -   source/drain regions in the substrate adjacent to the gate        structure.

An example second device embodiment of a floating gate non-volatilememory device comprises:

-   -   forming a bottom tunnel layer over a substrate;    -   a charge storage layer over the bottom tunnel layer;    -   a top blocking layer over the charge storage layer;    -   a gate electrode over the top blocking layer;    -   source/drain regions in the substrate adjacent to the gate        electrode.

The claims show other embodiments of the invention.

The above and below advantages and features are of representativeembodiments only, and are not exhaustive and/or exclusive. They arepresented only to assist in understanding the invention. It should beunderstood that they are not representative of all the inventionsdefined by the claims, to be considered limitations on the invention asdefined by the claims, or limitations on equivalents to the claims. Forinstance, some of these advantages may be mutually contradictory, inthat they cannot be simultaneously present in a single embodiment.Similarly, some advantages are applicable to one aspect of theinvention, and inapplicable to others. Furthermore, certain aspects ofthe claimed invention have not been discussed herein. However, noinference should be drawn regarding those discussed herein relative tothose not discussed herein other than for purposes of space and reducingrepetition. Thus, this summary of features and advantages should not beconsidered dispositive in determining equivalence. Additional featuresand advantages of the invention will become apparent in the followingdescription, from the drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of a semiconductor device according to thepresent invention and further details of a process of fabricating such asemiconductor device in accordance with the present invention will bemore clearly understood from the following description taken inconjunction with the accompanying drawings in which like referencenumerals designate similar or corresponding elements, regions andportions and in which:

FIG. 1 is a cross sectional view for illustrating a method formanufacturing memory device according to a first example embodiment ofthe present invention.

FIG. 2 is a cross sectional view for illustrating a method formanufacturing memory device according to a second example embodiment ofthe present invention.

FIG. 3 is a flowchart for illustrating a method for manufacturing memorydevice according to the first example embodiment of the presentinvention.

FIG. 4 is a flowchart for illustrating a method for manufacturing memorydevice according to the second example embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS I. Overview of ExampleEmbodiments

The present invention will be described in detail with reference to theaccompanying drawings. The present invention provides structures andmethod of forming a memory device.

II. First Example Embodiment

The first example embodiment of a memory structure is depicted inFIG. 1. It preferably employs a top blocking layer 40 comprised ofSiO₂/HfO₂ 38 34, a charge storage layer 32 comprised of Ta₂O₅, and abottom tunnel dielectric 28 comprised of HfO2/SiO₂ 26 22. The top andbottom SiO₂ 38 22 are preferably very thin, <1 nm. The ultra-thininterfacial SiO₂ layers serves to improve the retention and interfacialquality for the bottom Si and gate electrode. The HfO₂ layers canimprove the erase speed as compared to a conventional SONOS. The topHfO₂ layer 34 thickness preferably ranges from 5 to 20 nm, while thebottom HfO₂ layer 26 thickness preferably ranges from 1 to 6 nm. TheTa₂O₅ layer 30 preferably thickness ranges from 3 to 8 nm. Using high-kmaterials allow further device and voltage scaling. They can bedeposited using CVD or PVD processes. The gate electrode 44 can be metalor polysilicon.

A first example embodiment for a method of fabrication of a floatinggate non-volatile memory device is described below and shown in FIGS. 1and 3. FIG. 3 shows a flowchart of the steps.

A. Bottom Tunnel Layer

Referring to FIG. 1, we provide a semiconductor substrate 10. Thesubstrate can be any suitable semiconductor structure, such as a siliconwafer.

Referring to FIG. 1 and FIG. 3 (step S100), We form a bottom tunnellayer 28 (tunnel insulator) over a substrate 10.

The bottom tunnel layer 28 is preferably comprised of a lower oxidetunnel layer 22 and an upper hafnium oxide tunnel layer 26.

The lower oxide tunnel layer 22 is comprised essentially of siliconoxide and has a thickness between 0.2 nm and 1 nm and more preferablyabout 0.5 nm.

The upper hafnium oxide tunnel layer 26 is preferably comprisedessentially of hafnium oxide (HfO2) and has a thickness between 1 and 6nm and more preferably about 2.0 nm.

B. Bottom Layer Anneal Step

Referring to FIG. 3, step S104, in an tunnel anneal step, annealing thebottom tunnel layer 28 in a hydrogen containing atmosphere.

The tunnel anneal step comprises an anneal in a H containing atmosphere,such as NH₃ or H₂, at a temperature between about 300 and 450 degree C.for a time between 5 and 60 seconds.

A H containing anneal is employed prior to the charge trapping layerdeposition is important to enhance the bottom layer 28 and interfacequality. It is thought that the anneal passivates the Si Dangling bondsat the interface. This in turn improves the retention and endurance ofthe memory device. It is thought that performing the anneal after thedeposition of the overlying charge storage layer is not sufficientlyeffective due to the H blockage by the charge storage layer.

-   -   C. Charge Storage Layer

Referring to FIGS. 1 and 3 (step S108) we form a charge storage layer 32(charge trapping layer) over the bottom tunnel layer 28.

The charge storage layer 32 is comprised of a tantalum oxide layer 30.The tantalum oxide layer is comprised essentially of tantalum oxide andhas a thickness between 3 and 8 nm and more preferably about 5 nm.

-   -   D. Charge Trapping Layer Anneal Step

Referring to FIG. 3 (step S112) in the storage anneal step, we annealthe charge storage layer 30 and the bottom tunnel layer 28 in a nitrogencontaining atmosphere.

The charge trapping layer anneal step preferably comprises an anneal ina nitrogen containing atmosphere, such as N or NH₃, at a temperaturebetween about 300 and 450 degree C. for a time between 15 and 60seconds. It is thought that the charge trapping layer anneal stepeliminates defects in the Ta₂O₅ layer and improves its trappingcapability.

Overall, it is thought that the first tunnel anneal improves the dateretentions capabilities and the second charge trapping layer anneal stepimproves the charge trapping capabilities.

E. Top Blocking Layer

Referring to FIGS. 1 and 3 (steps S116, S120 and S124) we form a topblocking layer (blocking insulator) 40 over the charge storage layer 32.

The top blocking layer 40 is preferably comprised of a lower hafniumoxide (blocking) layer 34 and an upper oxide (blocking) layer 38. Ananneal can be performed between the formation of the lower hafnium oxidelayer 34 and the upper oxide layer 38 as shown in FIG. 3.

The lower hafnium oxide layer 34 is preferably comprised essentially ofhafnium oxide and preferably has a thickness between 5 and 20 nm.

-   -   F. Blocking Layer Anneal Step

Referring to FIG. 3, step S120, in the blocking layer anneal step, weanneal the lower hafnium oxide storage layer 34 in a nitrogen containingatmosphere.

The block anneal step comprises an anneal in a nitrogen or ammoniacontaining atmosphere, at a temperature between about 300 and 450 degreeC. for a time between 15 and 60 seconds.

The blocking layer anneal step is thought to densify the hafnium oxide34 thus improving it's blocking capability.

G. Upper Oxide Cap Layer

Referring to FIG. 1 and FIG. 3 (step S124), we form the upper oxide caplayer 38.

The upper oxide cap storage layer 38 is preferably comprised essentiallyof silicon oxide and has a thickness between 0.2 and 1 nm and morepreferably about 0.5 nm.

H. A Gate Electrode

Referring to FIG. 1, we form a gate electrode 44 over the top blockinglayer 40. The gate electrode 44 is preferably comprised of polysiliconor metal and preferably has thickness between 800 and 2000 Å.

I. Form a Gate Structure

Next, as shown in FIG. 1, we pattern the bottom tunnel layer 28, thecharge storage layer 32, and top blocking layer 40 to form a gatestructure 50.

J. Source/Drain Regions

Next, we form source/drain regions 14 in the substrate 10 adjacent tothe gate structure 50. Preferably the source drain regions are formed byan implant process.

K. Non-Limiting Features of the 1^(st) Embodiment

The first embodiment of the present invention will improve the retentionand erase speed over the conventional SONOS, and suitable for furtherdevice and voltage scaling.

The retentions and erase speed are improved because

(1) band gap engineer—the lower barrier height of hafnium oxide and thedeep trap energy level of Ta₂O₅.

(2) the three annealing steps—The first anneal improves the interfacequality. The second anneal step improves the charge trapping capabilityby eliminating the defects in the dielectric. The third anneal stepimproves the blocking layer integrity by denisfying the hafnium oxidefilm.

III. Second Example Embodiment

A second example embodiment is shown in FIG. 2 and the flowchart in FIG.4. Corresponding layers and process can be carried out as describedabove in the first example embodiment.

The second example embodiment of a memory structure is depicted in FIG.2. It preferably employs a top blocking layer 240 comprised of SiO₂, acharge storage layer 232 comprised of Ta₂O₅, and a bottom tunneldielectric 228 comprised of SiO₂. The gate electrode 244 can be metal orpolysilicon.

A. A Bottom Tunnel Layer

We provide a substrate. We form a bottom tunnel layer 228 over asubstrate 210.

The bottom tunnel layer 228 is preferably comprised essentially ofsilicon oxide and has a thickness between 1 and 4 nm and more preferablyabout 2 nm.

B. Bottom Layer Anneal Step

Referring to FIG. 4, step 204, in an optional tunnel nitridation step,annealing the bottom tunnel layer 28 in a nitrogen and hydrogencontaining atmosphere.

The tunnel anneal step preferably comprises an anneal in a nitrogen orammonia containing atmospheres, at a temperature between about 300 and450 degree C. for a time between 15 and 60 seconds.

The H in the anneal step will passivate the interface. The slightnitridation will be beneficial to improve device reliability due to hotcarrier effects.

C. Form a Charge Storage Layer

Next, we form a charge storage layer 232 over the a bottom tunnel layer28.

The charge storage layer 232 is preferably comprised of a tantalum oxidelayer. The tantalum oxide layer is comprised essentially of tantalumoxide and has a thickness between 3 and 8 nm and more preferably about 5nm.

D. A Charge Trapping Layer Anneal Step

Referring to FIG. 4, step S208, in a charge trapping layer anneal step,annealing charge storage layer 232 in a nitrogen containing atmosphere.

The storage anneal step preferably comprises an anneal in a nitrogen orammonia containing atmosphere, at a temperature between about 300 and450 degree C. for a time between 15 and 60 seconds; the RF power rangesfrom 100 to 500 W (more preferably about 300 W; and the pressure rangesform 5 to 30 mtrr and more preferably about 10 mtorr.

The effects of the anneal are similar as describe above in the firstembodiment.

E. Top Blocking Layer

Next, we form a top blocking layer 240 over the charge storage layer232. The top blocking layer 240 is preferably comprised essentially ofsilicon oxide and has a thickness between 2 and 10 nm.

F. A Plasma Nitridation Step

Referring to FIG. 4, (step S212, a block nitridation) in a plasmanitridation step, we nitridate the top blocking layer 240 in a nitrogencontaining atmosphere. A preferably thin top silicon nitride layer 241is formed on the surface of the top blocking layer 40.

The top silicon nitride layer 241 is most likely an atomic thickness.

The block nitridation step preferably comprises an anneal in a nitrogenor ammonia containing atmosphere, at a temperature between about 300 and500 degree C. and more preferably about 350 C.; for a time between 20and 60 seconds.

The plasma nitridation step serves to add a thin layer of siliconnitride on the top the SiO₂ . This improves the blocking capitilites.

G. Gate Electrode

We form a gate electrode 244 over the top blocking layer 240. The gateelectrode is preferably comprised of polysilicon and preferably has athickness between 800 and 2000 Å.

H. Gate Structure

As shown in FIG. 2, we pattern the bottom tunnel layer 228, the chargestorage layer 232, and top blocking layer 240 and the gate electrode 244to form a gate structure 250.

I. Source/Drain Regions

As shown in FIG. 2, we form source/drain regions 214 in the substrate 10adjacent to the gate structure 250. This completes the memory device.

J. Features of the Second Embodiment

The second embodiment of the present invention will improve theretention and erase speed over the conventional SONOS, and suitable forfurther device and voltage scaling.

The embodiments improve retention because:

-   1) Increase trap density and deep level traps in Ta₂O₅.-   2) The anneal between the Ta₂O₅ and bottom layers help to passivate    the Si dangling bonds at the interface. The slight nitridation also    improve reliability and hardness.-   3) The second anneal after Ta502 improve the film quality and    improve the stability.-   4) The last anneal adds nitrided layer to improve the blocking    capability to reduce over erase issues.

K. Non-Limiting Embodiments

In the above description numerous specific details are set forth such asflow rates, pressure settings, thicknesses, etc., in order to provide amore thorough understanding of the present invention. Those skilled inthe art will realize that power settings, residence times, gas flowrates are equipment specific and will vary from one brand of equipmentto another. It will be obvious, however, to one skilled in the art thatthe present invention may be practiced without these details. In otherinstances, well known process have not been described in detail in orderto not unnecessarily obscure the present invention.

Unless explicitly stated otherwise, each numerical value and rangeshould be interpreted as being approximate as if the word about orapproximately preceded the value of the value or range.

Given the variety of embodiments of the present invention justdescribed, the above description and illustrations show not be taken aslimiting the scope of the present invention defined by the claims.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention. It isintended to cover various modifications and similar arrangements andprocedures, and the scope of the appended claims therefore should beaccorded the broadest interpretation so as to encompass all suchmodifications and similar arrangements and procedures.

1. A method of fabricating a device comprising: providing a substrate;forming a tunneling layer on the substrate; annealing the tunnelinglayer; forming a charge storage layer over the tunneling layer, whereinthe charge storage layer comprises a metal oxide; and forming a blockinglayer over the charge storage layer.
 2. The method of claim 1 whereinthe metal oxide layer comprises a transitional metal.
 3. The method ofclaim 1 wherein the tunneling layer comprises a tunneling stack having atunneling dielectric layer and a metal oxide layer.
 4. The method ofclaim 1 wherein the blocking layer comprises a blocking stack having adielectric layer and a metal oxide layer.
 5. A method of forming amemory device comprising: providing a substrate prepared with atunneling layer; annealing the tunneling layer; forming a charge storagelayer above the tunneling layer, wherein the charge storage layercomprises a metal oxide; annealing the charge storage layer in anitrogen containing atmosphere; forming a blocking layer above thecharge storage layer; and forming a gate electrode layer above theblocking layer.